The present invention is directed toward semiconductor circuits, and more particularly to complementary semiconductor-on-insulator lateral bipolar SRAM circuits and methods for fabrication such circuits.
Digital logic has been dominated by silicon complementary metal-oxide-semiconductor (CMOS) circuits. However, it is becoming increasingly difficult to fabricate CMOS circuitry that meets technology's demand for ever smaller devices that operate using less power. For example, the performance of static random access memory (SRAM) implemented in CMOS is reaching a limit due to its poor signal-to-noise margins at low operating voltages (i.e., less than 0.5 V).
Using bipolar transistors to construct SRAM cells offers lower standby power and large static noise margin. However, conventional vertical bipolar transistors are generally not suitable for high density digital logic because of their large footprint due to isolation structure, and their large parasitic capacitance due to minority carrier charge storage.